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R_CUDA Relocation Catalog

Complete reference table of all 119 R_CUDA relocation type names extracted from nvlink v13.0.88. Types are organized into two descriptor tables: the standard table at off_1D37600 (117 entries, indices 0--116) and the attribute table at off_1D371E0 (65 entries, indices 0x10000--0x10040). See R_CUDA Relocations for the relocation engine, descriptor format, action types, and architecture class system.

Standard Table (off_1D37600)

117 entries. Index = raw r_type value in .rela.* sections. Bit width and bit position are derived from the type name and confirmed against the 64-byte descriptors at off_1D3DBE0.

IndexNameTypeBit WidthBit Position
0R_CUDA_NONEsentinel----
1R_CUDA_32data320
2R_CUDA_64data640
3R_CUDA_G32global320
4R_CUDA_G64global640
5R_CUDA_ABS32_26abs-instr3226
6R_CUDA_TEX_HEADER_INDEXtexturespecialspecial
7R_CUDA_SAMP_HEADER_INDEXsamplerspecialspecial
8R_CUDA_SURF_HW_DESCsurfacespecialspecial
9R_CUDA_SURF_HW_SW_DESCsurfacespecialspecial
10R_CUDA_ABS32_LO_26abs-instr1626
11R_CUDA_ABS32_HI_26abs-instr1626
12R_CUDA_ABS32_23abs-instr3223
13R_CUDA_ABS32_LO_23abs-instr1623
14R_CUDA_ABS32_HI_23abs-instr1623
15R_CUDA_ABS24_26abs-instr2426
16R_CUDA_ABS24_23abs-instr2423
17R_CUDA_ABS16_26abs-instr1626
18R_CUDA_ABS16_23abs-instr1623
19R_CUDA_TEX_SLOTtexturespecialspecial
20R_CUDA_SAMP_SLOTsamplerspecialspecial
21R_CUDA_SURF_SLOTsurfacespecialspecial
22R_CUDA_TEX_BINDLESSOFF13_32bindless1332
23R_CUDA_TEX_BINDLESSOFF13_47bindless1347
24R_CUDA_CONST_FIELD19_28const1928
25R_CUDA_CONST_FIELD19_23const1923
26R_CUDA_TEX_SLOT9_49texture949
27R_CUDA_6_31misc631
28R_CUDA_2_47misc247
29R_CUDA_TEX_BINDLESSOFF13_41bindless1341
30R_CUDA_TEX_BINDLESSOFF13_45bindless1345
31R_CUDA_FUNC_DESC32_23func-desc3223
32R_CUDA_FUNC_DESC32_LO_23func-desc1623
33R_CUDA_FUNC_DESC32_HI_23func-desc1623
34R_CUDA_FUNC_DESC_32func-desc320
35R_CUDA_FUNC_DESC_64func-desc640
36R_CUDA_CONST_FIELD21_26const2126
37R_CUDA_QUERY_DESC21_37misc2137
38R_CUDA_CONST_FIELD19_26const1926
39R_CUDA_CONST_FIELD21_23const2123
40R_CUDA_PCREL_IMM24_26pc-rel2426
41R_CUDA_PCREL_IMM24_23pc-rel2423
42R_CUDA_ABS32_20abs-instr3220
43R_CUDA_ABS32_LO_20abs-instr1620
44R_CUDA_ABS32_HI_20abs-instr1620
45R_CUDA_ABS24_20abs-instr2420
46R_CUDA_ABS16_20abs-instr1620
47R_CUDA_FUNC_DESC32_20func-desc3220
48R_CUDA_FUNC_DESC32_LO_20func-desc1620
49R_CUDA_FUNC_DESC32_HI_20func-desc1620
50R_CUDA_CONST_FIELD19_20const1920
51R_CUDA_BINDLESSOFF13_36bindless1336
52R_CUDA_SURF_HEADER_INDEXsurfacespecialspecial
53R_CUDA_INSTRUCTION64instr640
54R_CUDA_CONST_FIELD21_20const2120
55R_CUDA_ABS32_32abs-instr3232
56R_CUDA_ABS32_LO_32abs-instr1632
57R_CUDA_ABS32_HI_32abs-instr1632
58R_CUDA_ABS47_34abs-instr4734
59R_CUDA_ABS16_32abs-instr1632
60R_CUDA_ABS24_32abs-instr2432
61R_CUDA_FUNC_DESC32_32func-desc3232
62R_CUDA_FUNC_DESC32_LO_32func-desc1632
63R_CUDA_FUNC_DESC32_HI_32func-desc1632
64R_CUDA_CONST_FIELD19_40const1940
65R_CUDA_BINDLESSOFF14_40bindless1440
66R_CUDA_CONST_FIELD21_38const2138
67R_CUDA_INSTRUCTION128instr1280
68R_CUDA_YIELD_OPCODE9_0yield90
69R_CUDA_YIELD_CLEAR_PRED4_87yield487
70R_CUDA_32_LOdata160
71R_CUDA_32_HIdata160
72R_CUDA_UNUSED_CLEAR32clear320
73R_CUDA_UNUSED_CLEAR64clear640
74R_CUDA_ABS24_40abs-instr2440
75R_CUDA_ABS55_16_34abs-instr5534
76R_CUDA_8_0byte80
77R_CUDA_8_8byte88
78R_CUDA_8_16byte816
79R_CUDA_8_24byte824
80R_CUDA_8_32byte832
81R_CUDA_8_40byte840
82R_CUDA_8_48byte848
83R_CUDA_8_56byte856
84R_CUDA_G8_0global80
85R_CUDA_G8_8global88
86R_CUDA_G8_16global816
87R_CUDA_G8_24global824
88R_CUDA_G8_32global832
89R_CUDA_G8_40global840
90R_CUDA_G8_48global848
91R_CUDA_G8_56global856
92R_CUDA_FUNC_DESC_8_0func-desc80
93R_CUDA_FUNC_DESC_8_8func-desc88
94R_CUDA_FUNC_DESC_8_16func-desc816
95R_CUDA_FUNC_DESC_8_24func-desc824
96R_CUDA_FUNC_DESC_8_32func-desc832
97R_CUDA_FUNC_DESC_8_40func-desc840
98R_CUDA_FUNC_DESC_8_48func-desc848
99R_CUDA_FUNC_DESC_8_56func-desc856
100R_CUDA_ABS20_44abs-instr2044
101R_CUDA_SAMP_HEADER_INDEX_0samplerspecialspecial
102R_CUDA_UNIFIEDunifiedspecialspecial
103R_CUDA_UNIFIED_32unified320
104R_CUDA_UNIFIED_8_0unified80
105R_CUDA_UNIFIED_8_8unified88
106R_CUDA_UNIFIED_8_16unified816
107R_CUDA_UNIFIED_8_24unified824
108R_CUDA_UNIFIED_8_32unified832
109R_CUDA_UNIFIED_8_40unified840
110R_CUDA_UNIFIED_8_48unified848
111R_CUDA_UNIFIED_8_56unified856
112R_CUDA_UNIFIED32_LO_32unified1632
113R_CUDA_UNIFIED32_HI_32unified1632
114R_CUDA_ABS56_16_34abs-instr5634
115R_CUDA_CONST_FIELD22_37const2237
116R_CUDA_NONE_LASTsentinel----

Attribute Table (off_1D371E0)

65 entries. Attribute relocations apply to .nv.info.* metadata sections rather than instruction streams. The encoded r_type in ELF is 0x10000 + index (e.g., attribute index 3 = r_type 0x10003). The attribute table reuses a subset of the same type names as the standard table but with different 64-byte descriptors.

The attribute table entries are not individually named in the binary -- they share string pointers with the standard table. The following mapping lists the 65 attribute indices and the standard-table name each one references. Indices not listed here (gaps) use R_CUDA_NONE.

Attr Indexr_typeShared NameType
00x10000R_CUDA_NONEsentinel
10x10001R_CUDA_32data
20x10002R_CUDA_64data
30x10003R_CUDA_G32global
40x10004R_CUDA_G64global
50x10005R_CUDA_ABS32_26abs-instr
60x10006R_CUDA_TEX_HEADER_INDEXtexture
70x10007R_CUDA_SAMP_HEADER_INDEXsampler
80x10008R_CUDA_SURF_HW_DESCsurface
90x10009R_CUDA_SURF_HW_SW_DESCsurface
100x1000AR_CUDA_ABS32_LO_26abs-instr
110x1000BR_CUDA_ABS32_HI_26abs-instr
120x1000CR_CUDA_ABS32_23abs-instr
130x1000DR_CUDA_ABS32_LO_23abs-instr
140x1000ER_CUDA_ABS32_HI_23abs-instr
150x1000FR_CUDA_ABS24_26abs-instr
160x10010R_CUDA_ABS24_23abs-instr
170x10011R_CUDA_ABS16_26abs-instr
180x10012R_CUDA_ABS16_23abs-instr
190x10013R_CUDA_TEX_SLOTtexture
200x10014R_CUDA_SAMP_SLOTsampler
210x10015R_CUDA_SURF_SLOTsurface
220x10016R_CUDA_TEX_BINDLESSOFF13_32bindless
230x10017R_CUDA_TEX_BINDLESSOFF13_47bindless
240x10018R_CUDA_CONST_FIELD19_28const
250x10019R_CUDA_CONST_FIELD19_23const
260x1001AR_CUDA_TEX_SLOT9_49texture
270x1001BR_CUDA_6_31misc
280x1001CR_CUDA_2_47misc
290x1001DR_CUDA_TEX_BINDLESSOFF13_41bindless
300x1001ER_CUDA_TEX_BINDLESSOFF13_45bindless
310x1001FR_CUDA_FUNC_DESC32_23func-desc
320x10020R_CUDA_FUNC_DESC32_LO_23func-desc
330x10021R_CUDA_FUNC_DESC32_HI_23func-desc
340x10022R_CUDA_FUNC_DESC_32func-desc
350x10023R_CUDA_FUNC_DESC_64func-desc
360x10024R_CUDA_CONST_FIELD21_26const
370x10025R_CUDA_QUERY_DESC21_37misc
380x10026R_CUDA_CONST_FIELD19_26const
390x10027R_CUDA_CONST_FIELD21_23const
400x10028R_CUDA_PCREL_IMM24_26pc-rel
410x10029R_CUDA_PCREL_IMM24_23pc-rel
420x1002AR_CUDA_ABS32_20abs-instr
430x1002BR_CUDA_ABS32_LO_20abs-instr
440x1002CR_CUDA_ABS32_HI_20abs-instr
450x1002DR_CUDA_ABS24_20abs-instr
460x1002ER_CUDA_ABS16_20abs-instr
470x1002FR_CUDA_FUNC_DESC32_20func-desc
480x10030R_CUDA_FUNC_DESC32_LO_20func-desc
490x10031R_CUDA_FUNC_DESC32_HI_20func-desc
500x10032R_CUDA_CONST_FIELD19_20const
510x10033R_CUDA_BINDLESSOFF13_36bindless
520x10034R_CUDA_SURF_HEADER_INDEXsurface
530x10035R_CUDA_INSTRUCTION64instr
540x10036R_CUDA_CONST_FIELD21_20const
550x10037R_CUDA_ABS32_32abs-instr
560x10038R_CUDA_ABS32_LO_32abs-instr
570x10039R_CUDA_ABS32_HI_32abs-instr
580x1003AR_CUDA_ABS47_34abs-instr
590x1003BR_CUDA_ABS16_32abs-instr
600x1003CR_CUDA_ABS24_32abs-instr
610x1003DR_CUDA_FUNC_DESC32_32func-desc
620x1003ER_CUDA_FUNC_DESC32_LO_32func-desc
630x1003FR_CUDA_FUNC_DESC32_HI_32func-desc
640x10040R_CUDA_CONST_FIELD19_40const

Category Summary

TypeCount (standard)Description
abs-instr25Absolute address patched into instruction bit-fields
bindless6Bindless texture/surface offset
byte8Byte-granularity data patching (R_CUDA_8_*)
clear2Zero-fill unused fields
const10Constant bank offset (R_CUDA_CONST_FIELD*)
data4Full-width data-section relocations (32, 64, 32_HI, 32_LO)
func-desc19Function descriptor reference
global10Global memory address (R_CUDA_G*)
instr2Whole-instruction replacement (64-bit or 128-bit)
misc3Query descriptor, narrow-field encodings
pc-rel2PC-relative branch offset
sampler3Sampler header/slot binding
sentinel2No-op / end-of-range marker
surface4Surface header/slot/descriptor binding
texture3Texture header/slot binding
unified12Unified descriptor/function table reference
yield2YIELD-to-NOP instruction conversion
Total117

Cross-References

Confidence Assessment

Verification scope: All 117 standard-table names and 65 attribute-table indices were cross-checked against nvlink_strings.json (exact-string match) and the decompiled table dispatcher sub_42F6C0 (nvlink/decompiled/sub_42F6C0_0x42f6c0.c). Ten entries were spot-checked end-to-end: string presence, string address, and relocation-engine consumption of off_1D3DBE0.

Totals: 117 standard entries + 65 attribute entries = 182 catalog rows. String verification: 119 / 119 raw strings in nvlink_strings.json (includes two trailing-whitespace duplicates of R_CUDA_UNIFIED_8_0 and R_CUDA_UNIFIED_8_8 at 0x1d3cb9f / 0x1d3cbb3) collapse to the 117 canonical names after trimming. Verified: 117 / 117 canonical names. Unverified: 0.

Spot-check table (10 entries)

EntryConfidenceEvidence
R_CUDA_NONE (idx 0)HIGHString at 0x1D35F60 (nvlink_strings.json); dispatched via off_1D37600[0] in sub_42F6C0 (line 25); sentinel no-op path in relocation engine
R_CUDA_G64 (idx 4)HIGHString at 0x1D35F8B; reachable via off_1D37600[4] in sub_42F6C0; descriptor consumed by sub_469620 (line 27: v8 = &off_1D3DBE0)
R_CUDA_TEX_HEADER_INDEX (idx 6)HIGHString at 0x1D35FA6; texture-binding path in bindless relocation engine
R_CUDA_CONST_FIELD19_28 (idx 24)HIGHString at 0x1D36108; 19-bit bitfield encoding at position 28 matches the name suffix
R_CUDA_FUNC_DESC_32 (idx 34)HIGHString at 0x1D361E4; descriptor table entry consumed by sub_46ADC0 (line 135: v90 = &off_1D3DBE0) -- resolved relocations emitter
R_CUDA_PCREL_IMM24_26 (idx 40)HIGHString at 0x1D3626B; PC-relative branch handler in relocation engine
R_CUDA_INSTRUCTION64 (idx 53)HIGHString at 0x1D3637E; whole-instruction replacement path in sub_469D60 (line 214: v152 = &off_1D3DBE0)
R_CUDA_BINDLESSOFF14_40 (idx 65)HIGHString at 0x1D36471; bindless-offset handler in texture relocation pipeline
R_CUDA_YIELD_OPCODE9_0 (idx 68)HIGHString at 0x1D364B7; YIELD-opcode rewrite path in sub_469D60; cross-referenced in ptxas wiki (relocations.md line 244)
R_CUDA_NONE_LAST (idx 116)HIGHString at 0x1D36808; end-of-range sentinel -- bounds a1 >= 0x75 check in sub_42F6C0 (line 26)

Cross-reference with the ptxas Relocations page: The ten spot-checked names match verbatim against ptxas lines 80, 124, 140, 155, 179, 195, 217, 242, 244, 248. No ordinal drift between ptxas and nvlink for these entries.

AspectConfidenceBasis
Type names (all 117 entries)HIGH117/117 canonical names found in nvlink_strings.json at addresses 0x1D35F60--0x1D36808 (contiguous string-pool region); no missing entries
Standard table address (off_1D37600)HIGHConfirmed in decompiled sub_42F6C0 line 25 (v7 = &off_1D37600); bounds check a1 >= 0x75 (117 = 0x75) at line 26
Attribute table address (off_1D371E0)HIGHConfirmed in decompiled sub_42F6C0 line 17 (v7 = &off_1D371E0); bounds check a1 < 0x41 (65 = 0x41) at line 18 after a1 -= 0x10000
Descriptor table address (off_1D3DBE0)HIGHReferenced by three relocation engines: sub_469620 (line 27), sub_46ADC0 (line 135), sub_469D60 (line 214)
Entry count (117 standard, 65 attribute)HIGHTable bounds encoded as immediate constants in sub_42F6C0: v6 = 117 (line 24) and v6 = 65 (line 16)
Index-to-name mappingHIGHName strings are stored as 16-byte records (ptr, 3xDWORD metadata) at off_1D37600; sub_42F6C0 line 29: v8 = &v7[2 * a1] confirms 16-byte stride
Bit width / bit position columnsMEDIUMParsed by this catalog from type-name suffix convention (ABS32_26 = 32-bit field at bit 26); the 64-byte descriptors at off_1D3DBE0 encode these values but were not byte-for-byte decoded for every entry
Category classificationMEDIUMInferred from naming patterns (ABS = absolute, PCREL = PC-relative, CONST_FIELD = constant bank, FUNC_DESC = function descriptor, etc.); no explicit category field in the binary
Attribute table shared-name mappingMEDIUMAttribute entries at off_1D371E0 share string pointers with the standard table at off_1D37600 by pointer equality; the 1:1 index mapping is inferred from array position, not from an explicit mapping table. Gaps in the attribute table (e.g. indices beyond 0x40) fall through to the "unknown attribute" diagnostic at sub_42F6C0 line 21
Action-code bit-field interpretationLOWThe 64-byte descriptor layout at off_1D3DBE0 (bit width, shift, action enum, arch-class bitmask) is inferred from consumer code patterns in sub_469620/sub_46ADC0/sub_469D60, not documented as a concrete struct in the binary